1. Field of the Invention
The present invention relates to a method of forming a self-aligned thyristor, and more particularly, to a method of forming a self-aligned thyristor compatible with MOS transistor fabrication processes and capable of saving a thyristor layout area.
2. Description of the Prior Art
A thyristor is a switching application element capable of being applied to switching to a conductive state from a broken circuit state. The thyristor comprises a three junction P1N1P2N2 electric element. A node contact connected to P1 is an anode, and a node contact connecting to N2 is a cathode. If a gate is added at P2, then the thyristor is called a semiconductor-controlled rectifier (SCR), such as described in US. Pat. Nos. 5,225,702, and 5,682,047.
FIG. 1 is a structure diagram of a prior art thyristor 30 used in a static electricity protection circuit. As shown in FIG. 1, the prior art thyristor 30 is formed on a semiconductor chip 10. The thyristor 30 comprises a silicon substrate 12, a P-well 14 deposited on the silicon substrate 12, corresponding to the above-mentioned P1, an N+ area 16 deposited in the P-well 14, corresponding to the above-mentioned N1, an N-well 18 deposited on the silicon substrate 12 and adjacent to the P-well 14, corresponding to the above-mentioned N2, a P+ area 20 deposited in the N-well 18, corresponding to the above-mentioned P2, and a gate 22 deposited on the P-well 14 at a right side of the N+ area 16. It should be clear to one of ordinary skill in the art that the thyristor 30 has a structure similar to that of a complementary metal-oxide semiconductor (CMOS).
The P-well 14 further comprises a P+ area 15 deposited at a left side of the N+ area 16, and the N-well 18 further comprises an N+ area 19 deposited at a right side of the P+ area 20. Between the P-well 14 and the N-well 18 is deposited an N+ area 21, and the N+ area 21 and the N+ area 16 are used as a source and a drain of the gate 22. Additionally, at the left of the P+ area 15, between the P+ area 15 and the N+ area 16, between the N+ area 16 and the N+ area 21 (under the gate 22), between the N+ area 21 and the P+ area 20, between the P+ area 20 and the N+ area 19, and at the right side of the N+ area 19, field oxide is deposited to perform isolation.
In the prior art, the P+ area 15 and the N+ area 16 are electrically connected to an anode 24 with multilevel interconnects 23, and the P+ area 20 and the N+ area 19 are electrically connected to a cathode 26 with multilevel interconnects 25. The gate 22 is also electrically connected to the cathode 26 by the multilevel interconnects 25. The above-mentioned thyristor 30 is deposited between an I/O device (not shown) and a pad (not shown) to avoid static electricity destroying a product in the pad.
The thyristor is a bipolar device with characteristics of being bistable and having a negative differential resistance (NDR), so it can also be used as a static random access memory (SRAM), such as described in U.S. Pat. No. 6,128,216.
Please refer to FIG. 2. FIG. 2 is a characteristic diagram of a current-voltage relationship of the thyristor 30. The cross axle is voltage, and the vertical axle is current. 31-32 is a reverse breakdown region, 32-33 is a reverse blocking region, 33-34 is a forward blocking region, 34-35 is an NDR region, and 35-36 is a forward conducting region. The SRAM with the characteristic of having negative differential resistance is operating in the NDR region 34-35 shown in FIG. 2.
However, in contrast with a dynamic random access memory (DRAM), integration of the SRAM is not high. Therefore, if the structure of the prior art thyristor 30 (similar with the structure of the complementary metal-oxide semiconductor, having both P-well 14 and N-well 18) is used as SRAM, the thyristor 30 occupies a large layout area, and does not raise integration. To solve this problem, as described in above-mentioned U.S. Pat. No. 6,128,216, two PNPN diodes share an N-type area to increase integration. However, the process is complicated, and different from the present invention.
It is therefore a primary objective of the present invention to provide a self-aligned thyristor that raises integration of an SRAM.
Another objective of the present invention is to provide a method of forming a self-aligned thyristor.
According to claimed invention, a doped well region is of a first conductivity type. A gate stacking structure is formed on the doped well region. The gate stacking structure comprises an isolating layer formed on the semiconductor substrate, a conductive layer deposited on the isolating layer, and a passivation layer deposited on the conductive layer. The gate stacking structure divides the doped well region into a first area and a second area. A first ion implantation process of a second conductivity type is performed to form a first doped area in the first area. A second ion implantation process of a second conductivity type is then performed to form a second doped area in the second area. A doping concentration of the second doped area is higher than a doping concentration of the first doped area. A spacer is formed on each side wall of the gate stacking structure. A dielectric layer is formed on the semiconductor substrate to cover the gate stacking structure, the spacer, the first doped area, and the second doped area. A via is formed on the dielectric layer above the first doped area. An in-situ doped poly-silicon layer of the first conductivity type dopant is formed on the dielectric layer. The first conductivity type dopant of the poly-silicon layer is thermally driven in to form a third doped area in the first doped area. A doping concentration of the third doped area is higher than a doping concentration of the semiconductor substrate.
It is an advantage of the present invention that integration of the SRAM is increased, and it is another advantage of the present invention that a Metal-Oxide-Semiconductor process can be used to form the thyristor.
These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.